In fabricating Damascene and Dual Damascene (DD) copper interconnects in accordance with prior art techniques, copper is encased in one or more copper diffusion barrier layers. Typically, Ta/TaNX is used as a barrier layer for sidewalls and at the bottom of long lines, and a relatively high-k dielectric layer, typically silicon nitride (or silicon carbide, or silicon oxide carbon nitride), is used as a top capping barrier layer. The use of a relatively high-k dielectric (such as silicon nitride) capping barrier layer is problematic, among other reasons, because: (a) such a high-k dielectric has poor adhesion to a copper surface, thereby impairing structural strength and integrity; and (b) it does not block interfacial copper diffusion at the interface between the copper and the silicon nitride.
As is well known, electromigration (EM) in copper interconnects is problematic because EM reduces reliability and leads to device failure. Because the copper surface diffusion activation energy (i.e., only about 0.7-0.9 eV) is lower than the copper bulk diffusion activation energy (i.e., about 1.2 eV), unbound interfacial copper atoms diffuse faster at the interface between copper and a silicon nitride capping layer than in the bulk copper. As a result, interfacial diffusion is largely responsible for electromigration (EM) in copper interconnects. Silicon nitride does not prevent or inhibit interfacial diffusion because silicon nitride has poor adhesion to copper, and does not effectively passivate (or immobilize) the top copper surface atoms. There have been attempts in the prior art to reduce interfacial diffusion by replacing silicon nitride. For example, to reduce surface diffuision at the top copper surface, in accordance with one prior art method, a top capping silicon nitride is replaced with, or preceded by, a selective, self-aligned, electroless deposited, metallic layer such as Pd, CoPX, CoWXPY, CoWXBY, or CoSnXPY. Such an electroless deposition process is problematic, among other reasons, because: (a) electroless deposition has (i) an erratic incubation (or initiation) period during which there is no deposition, and (ii) an erratic deposition rate due to inherent bath instability and aging; (b) non-selective spontaneous deposition on surrounding dielectrics which may result in bridging and/or increasing leakage current between conductor lines; (c) spontaneous deposition due to bath instability (i) on chamber walls, and (ii) in-situ in the bath; (d) contamination of exposed dielectric; and (e) deposited metal or alloy may have poor adhesion to a successively deposited dielectric layer, thereby impairing the structural strength and integrity of the device.
In light of the above, there is a need for methods and films that solve one or more of the above-identified problems.